1. Field of the Invention
The present invention relates to a method for manufacturing MOS type semiconductor devices, such as a power MOSFET, insulating gate type bipolar transistor, etc.
2. Description of the Prior Art
In MOS type semiconductor devices, a power MOSFET utilizing only majority carriers is known. Also, an insulated gate bipolar transistor (known as IGBT, IGT or COMFET) utilizing a conduction modulation caused by the two types of carriers, that is, electrons and holes is known.
One example of this type of semiconductor device is disclosed in U.S. Pat. Nos. 4,672,407 or 4,587,723.
FIG. 1 is a cross-sectional view showing a prior art power MOSFET which is usually manufactured by the following process steps. First, a p.sup.+ type diffused region 3 is formed in a surface of an n.sup.- type high resistivity layer 1 which constitutes a semiconductor substrate with an n.sup.+ type low resistivity layer 2. After forming a gate electrode 5 on the same surface of the n.sup.- type high resistivity layer 1 via a gate insulating film 41, an opening is formed in the gate electrode 5 by the photo-lithography method. An impurity diffusion for forming a p type base layer 6 is conducted by using the gate electrode 5 having the opening as a mask, and a p.sup.+ type low resistivity base layer region 7 is formed in the p type base layer 6 by photolithography and diffusion process steps.
Thereafter, by using again the gate electrode 5 as a part of a mask, an n.sup.+ type source layer 8 is formed, and the surfaces are covered by an insulating film 42. After forming a contact hoe in the insulating film 42, a source electrode 11 is formed, and also a drain electrode 12 contacted to the n.sup.+ type low resistivity layer 2 is formed.
In the semiconductor device thus constructed, when a positive voltage is applied to the gate electrode 5 with respect to the source electrode 11, a channel 9 is produced in a surface of the p type base layer 6 just under the gate insulating film 41, thereby causing a conductive state by injecting electron into the drain layer, consisting of the high resistivity layer 1 and the low resistivity layer 2, from the n.sup.+ type source layer 8 through the channel 9. When the potential of the gate electrode 5, is maintained at the same potential as the source electrode 11 or a negative voltage is applied relative to the source electrode 11, a non-conductive state is caused. Therefore, the abovedescribed device operates as a switching element.
FIG. 2 shows a prior art insulated gate type bipolar transistor (IGBT). The IGBT can be manufactured by using a semiconductor substrate consisting of a p.sup.+ type drain layer 10, an n.sup.+ type buffer layer 2 and an n.sup.- type high resistivity layer 1, through the same process steps as in the power MOSFET. The difference of the IGBT from the power MOSFET is as follows. When electrons are injected into the p.sup.+ type drain layer 10 from the n.sup.+ type source layer 8 through the channel 9, the n.sup.- type high resistivity layer 1 and the n.sup.+ type buffer layer 2, because the drain layer 10 is of p.sup.+ type layer, holes are injected into the n.sup.- type high resistivity layer 1 from the p.sup.+ type drain layer 10, in response to the injection of electrons, through the n.sup.+ type buffer layer 2. Therefore, the n.sup.- type high resistivity layer 1 changes its electrical conductance so as to have a low resistance.
When the MOSFET shown in FIG. 1 is turned off under a condition of connecting an inductive load as in an inverter circuit etc. the device is sometimes destroyed. The reason for such destruction will be explained by referring to FIG. 3. When the MOSFET is turned off under the inductive load, a depletion layer 22 is promptly produced at both sides of the PN junction 21. A portion of the hole carriers emitted at this time flows in a portion of the p type base layer 6 under the n.sup.+ type source layer 8 as a hole current 23. Because the surface of the p type base layer 6 and the n.sup.+ type source layer 8 are short-circuited by the source electrode 11, a potential difference calculated by multiplying the hole current 23 by a base resistance Rb is produced between the n.sup.+ type source layer 8 and the p type base layer 6. If the potential difference is greater than the built-in voltage between the base and source, a parasitic transistor consisting of the n.sup.+ type source layer 8, the p type base layer 6 and the n.sup.- type high resistivity layer 1 turns ON by injecting electrons from the source layer 8 to the p type base layer 6, thereby destroying the device.
An object for forming the p.sup.+ type diffused layer 3 is to prevent the device destruction due to the turning ON of the parasitic transistor by reducing the hole current 23 flowing under the n.sup.+ type source layer 8.
An object for forming the p.sup.+ type low resistivity base layer region 7 is to positively prevent the device destruction due to the turning ON of the parasitic transistor, that is, it intends to decrease the base resistance Rb mentioned above for preventing the turning ON of the parasitic transistor.
However, a sufficient turn-off capability in the power MOSFET under the inductive load is not obtained even though these counter measures are taken to meet the situation.
In case of the IGBT shown in FIG. 2 the device destruction is sometimes caused by the turning ON of the parasitic transistor consisting of the n.sup.+ type source layer 8, the p type base layer 6 and the n.sup.- type high resistivity layer 1 when a turn-off operation under the inductive load occurs as in the power MOSFET. Further, a more difficult problem is that the hole current 23 flowing under the n.sup.+ type source layer 8 exist, even in a normal ON state operation. Therefore, the IGBT is sometimes destroyed by the turning ON of the parasitic transistor even in a turn-off operation without an inductive load or even in the normal ON state operation. In the case of the IGBT as well as the power MOSFET, an effort has been conducted to prevent the ON state of the parasitic transistor by providing the p.sup.+ typed diffused layer 3 and p.sup.+ type low resistivity base layer region 7. However, the result is not sufficient.